{"id":8039,"date":"2025-10-18T17:41:49","date_gmt":"2025-10-18T09:41:49","guid":{"rendered":"https:\/\/topfastpcba.com\/?p=8039"},"modified":"2025-10-22T16:29:39","modified_gmt":"2025-10-22T08:29:39","slug":"pcb-four-layer-board-design","status":"publish","type":"post","link":"https:\/\/topfastpcba.com\/es\/pcb-four-layer-board-design\/","title":{"rendered":"Dise\u00f1o de placa de circuito impreso de cuatro capas"},"content":{"rendered":"<p>En la electr\u00f3nica de consumo, los equipos de control industrial y los sistemas digitales de alta velocidad, las placas de circuito impreso de cuatro capas son muy apreciadas por su excelente compatibilidad electromagn\u00e9tica (EMC), integridad de la alimentaci\u00f3n e integridad de la se\u00f1al.<\/p>\n\n\n\n<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_75 counter-hierarchy ez-toc-counter ez-toc-custom ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">\u00cdndice<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/topfastpcba.com\/es\/pcb-four-layer-board-design\/#4-Layer_PCB_Stackup_Structure\" >Estructura de apilamiento de PCB de 4 capas<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/topfastpcba.com\/es\/pcb-four-layer-board-design\/#Via_Design\" >V\u00eda Dise\u00f1o<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/topfastpcba.com\/es\/pcb-four-layer-board-design\/#PCB_Routing\" >Enrutamiento de PCB<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/topfastpcba.com\/es\/pcb-four-layer-board-design\/#Power_Integrity_Design\" >Dise\u00f1o de integridad de potencia<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/topfastpcba.com\/es\/pcb-four-layer-board-design\/#Design_Verification_Production_Preparation\" >Verificaci\u00f3n del dise\u00f1o y preparaci\u00f3n de la producci\u00f3n<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/topfastpcba.com\/es\/pcb-four-layer-board-design\/#Key_Design_Takeaways\" >Conclusiones clave sobre el dise\u00f1o<\/a><\/li><\/ul><\/nav><\/div>\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"4-Layer_PCB_Stackup_Structure\"><\/span><a href=\"https:\/\/topfastpcba.com\/es\/4-layer-pcb-manufacturing-process\/\">Placa de circuito impreso de 4 capas<\/a> Estructura apilada<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>El dise\u00f1o del apilamiento es la base del rendimiento de una placa de 4 capas. Un apilamiento inadecuado puede provocar diafon\u00eda de se\u00f1ales, ruido en la fuente de alimentaci\u00f3n e incumplimiento de las normas EMI.<\/p>\n\n\n\n<p><strong>1. Comparaci\u00f3n de esquemas cl\u00e1sicos de apilamiento<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Esquema 1 (recomendado)<\/strong>\n<ul class=\"wp-block-list\">\n<li>Capa superior: Capa de se\u00f1al<\/li>\n\n\n\n<li>Capa 2: Plano de tierra (GND)<\/li>\n\n\n\n<li>Capa 3: Plano de alimentaci\u00f3n (PWR)<\/li>\n\n\n\n<li>Capa inferior: Capa de se\u00f1al<\/li>\n\n\n\n<li><strong>Ventajas:<\/strong> El plano de tierra proporciona una referencia s\u00f3lida para las se\u00f1ales de la capa superior. Los planos de alimentaci\u00f3n y tierra adyacentes forman una capacitancia de desacoplamiento inherente.<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li><strong>Esquema 2<\/strong>\n<ul class=\"wp-block-list\">\n<li>Capa superior: Capa de se\u00f1al<\/li>\n\n\n\n<li>Capa 2: Plano de alimentaci\u00f3n<\/li>\n\n\n\n<li>Capa 3: Plano de tierra<\/li>\n\n\n\n<li>Capa inferior: Capa de se\u00f1al<\/li>\n\n\n\n<li><strong>Escenarios aplicables:<\/strong> Dispositivos de alta corriente (por ejemplo, controladores de motores). Tenga en cuenta los posibles cambios en el plano de referencia para las se\u00f1ales de la capa inferior.<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li><strong>Esquema 3 (Usar con precauci\u00f3n)<\/strong>\n<ul class=\"wp-block-list\">\n<li>Capa superior: plano de tierra<\/li>\n\n\n\n<li>Capa 2: Capa de se\u00f1al<\/li>\n\n\n\n<li>Capa 3: Capa de se\u00f1al<\/li>\n\n\n\n<li>Capa inferior: plano de potencia<\/li>\n\n\n\n<li><strong>Riesgos:<\/strong> Plano de tierra incompleto, rutas de retorno de se\u00f1al largas. Adecuado principalmente para placas de baja frecuencia con predominio de conectores.<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n\n\n\n<p><strong>2. Configuraci\u00f3n de los par\u00e1metros clave<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Espesor diel\u00e9ctrico:<\/strong> Recommended 0.1\u20130.2mm between signal and reference planes to enhance inter-layer coupling.<\/li>\n\n\n\n<li><strong>Peso del cobre:<\/strong> Outer layers 1oz (35\u03bcm), inner layers 0.5oz (17.5\u03bcm). Can increase to 2oz for high-current areas.<\/li>\n\n\n\n<li><strong>Dise\u00f1o de retroceso:<\/strong> Power planes should be indented 40\u201380mil relative to the ground plane (20H rule) to reduce edge radiation.<\/li>\n<\/ul>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"600\" height=\"402\" src=\"https:\/\/topfastpcba.com\/wp-content\/uploads\/2025\/10\/4-Layer-PCB.jpg\" alt=\"Placa de circuito impreso de 4 capas\" class=\"wp-image-8040\" srcset=\"https:\/\/topfastpcba.com\/wp-content\/uploads\/2025\/10\/4-Layer-PCB.jpg 600w, https:\/\/topfastpcba.com\/wp-content\/uploads\/2025\/10\/4-Layer-PCB-300x201.jpg 300w, https:\/\/topfastpcba.com\/wp-content\/uploads\/2025\/10\/4-Layer-PCB-18x12.jpg 18w, https:\/\/topfastpcba.com\/wp-content\/uploads\/2025\/10\/4-Layer-PCB-150x101.jpg 150w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><\/figure>\n<\/div>\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Via_Design\"><\/span>V\u00eda Dise\u00f1o<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Las v\u00edas son cruciales para las conexiones entre capas, pero introducen par\u00e1metros par\u00e1sitos que afectan a las se\u00f1ales de alta velocidad.<\/p>\n\n\n\n<p><strong>1. Mediante selecci\u00f3n de tipo<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>V\u00edas pasantes:<\/strong> Bajo coste, adecuado para se\u00f1ales est\u00e1ndar y conexiones de alimentaci\u00f3n.<\/li>\n\n\n\n<li><strong>V\u00edas ciegas\/enterradas:<\/strong> Se utiliza para el enrutamiento de escape BGA de alta densidad, pero aumenta el coste del proceso.<\/li>\n<\/ul>\n\n\n\n<p><strong>2. C\u00e1lculo de par\u00e1metros parasitarios<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Capacitancia par\u00e1sita:<\/strong><br><code>C \u2248 1.41\u03b5 \u00b7 T \u00b7 D1 \/ (D2 - D1)<\/code><br>\u00bfD\u00f3nde? <code>T<\/code> es el grosor de la tabla, <code>D1<\/code> es el di\u00e1metro del taladro, <code>D2<\/code> es el di\u00e1metro de la almohadilla.<\/li>\n\n\n\n<li><strong>Inductancia par\u00e1sita:<\/strong><br><code>L \u2248 5.08h [ln(4h \/ d) + 1]<\/code><br>\u00bfD\u00f3nde? <code>h<\/code> es a trav\u00e9s de la longitud, <code>d<\/code> es el di\u00e1metro del taladro.<\/li>\n<\/ul>\n\n\n\n<p><strong>3. Directrices de uso de Via<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>V\u00edas de alimentaci\u00f3n:<\/strong> Utilice v\u00edas m\u00e1s grandes (por ejemplo, 12 mil de di\u00e1metro\/16 mil de perforaci\u00f3n) y coloque varias en paralelo para reducir la impedancia.<\/li>\n\n\n\n<li><strong>V\u00edas de se\u00f1al:<\/strong> Prefiera v\u00edas m\u00e1s peque\u00f1as (por ejemplo, 8 mil de di\u00e1metro\/12 mil de perforaci\u00f3n). Evite la colocaci\u00f3n asim\u00e9trica en pares diferenciales.<\/li>\n\n\n\n<li><strong>V\u00edas t\u00e9rmicas:<\/strong> Colocar debajo de componentes que generan calor (por ejemplo, broca de 0,3 mm, paso de 1,5 mm).<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"PCB_Routing\"><\/span><a href=\"https:\/\/topfastpcba.com\/es\/pcb-routing-3w-principle\/\">Enrutamiento de PCB<\/a><span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p><strong>1. Procedimiento de enrutamiento<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Aborda primero las \u00e1reas dif\u00edciles:<\/strong> Comience el enrutamiento desde \u00e1reas complejas como BGA e interfaces de alta velocidad.<\/li>\n\n\n\n<li><strong>Manipulaci\u00f3n modular:<\/strong> Ruta por bloques funcionales (por ejemplo, MCU, memoria, circuitos anal\u00f3gicos) para evitar interferencias cruzadas.<\/li>\n\n\n\n<li><strong>Ruta de limpieza:<\/strong> Enrute las se\u00f1ales de baja velocidad en \u00faltimo lugar, optimizando la utilizaci\u00f3n del canal mediante el ajuste del ancho y el espaciado de las pistas.<\/li>\n<\/ul>\n\n\n\n<p><strong>2. Reglas cr\u00edticas de enrutamiento<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Control de impedancia:<\/strong>\n<ul class=\"wp-block-list\">\n<li>Single-ended: 50\u03a9. Differential pairs: 100\u03a9.<\/li>\n\n\n\n<li>Cons\u00edguelo ajustando el ancho de traza, el grosor diel\u00e9ctrico y la permitividad.<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li><strong>Manejo de se\u00f1ales de alta velocidad:<\/strong>\n<ul class=\"wp-block-list\">\n<li>Priorizar el enrutamiento de las se\u00f1ales de reloj en las capas internas, con referencia a un plano de tierra.<\/li>\n\n\n\n<li>Maintain length matching in differential pairs (\u22645mil tolerance).<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li><strong>Segmentaci\u00f3n del plano de potencia:<\/strong>\n<ul class=\"wp-block-list\">\n<li>Segmentar un \u00fanico plano de alimentaci\u00f3n en un m\u00e1ximo de 3 regiones (por ejemplo, 3,3 V, 5 V, 12 V).<\/li>\n\n\n\n<li>Use segmentation lines \u22650.5mm wide to prevent creepage issues.<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Power_Integrity_Design\"><\/span>Dise\u00f1o de integridad de potencia<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p><strong>1. Colocaci\u00f3n del condensador de desacoplamiento<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Selecci\u00f3n:<\/strong> 0.1\u03bcF ceramic capacitors (high-frequency) + 10\u03bcF tantalum capacitors (low-frequency).<\/li>\n\n\n\n<li><strong>Ubicaci\u00f3n:<\/strong> Position close to IC power pins (\u22643mm). Connect directly to power\/ground planes via vias.<\/li>\n<\/ul>\n\n\n\n<p><strong>2. Integridad del plano de tierra<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Evite dividir el plano de tierra con trazas de se\u00f1al para garantizar rutas de retorno de baja impedancia.<\/li>\n\n\n\n<li>Connect digital and analog grounds at a single point using a ferrite bead or 0\u03a9 resistor.<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Design_Verification_Production_Preparation\"><\/span>Verificaci\u00f3n del dise\u00f1o y preparaci\u00f3n de la producci\u00f3n<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p><strong>1. Lista de verificaci\u00f3n de la RDC<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Trace Width\/Spacing: General signals \u22656\/6mil, Power traces \u226512\/12mil.<\/li>\n\n\n\n<li>Drill-to-Copper Distance: \u22658mil to prevent short circuits.<\/li>\n<\/ul>\n\n\n\n<p><strong>2. Simulaci\u00f3n de integridad de la se\u00f1al<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Utilice herramientas como HyperLynx o Sigrity para comprobar el tiempo de subida, el oscilaci\u00f3n y la continuidad de la impedancia.<\/li>\n\n\n\n<li>C\u00e9ntrese en verificar los relojes, las se\u00f1ales diferenciales y la ondulaci\u00f3n de la fuente de alimentaci\u00f3n.<\/li>\n<\/ul>\n\n\n\n<p><strong>3. Salida del archivo de producci\u00f3n<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Proporcione archivos Gerber (incluye capas, m\u00e1scara de soldadura, taladro), cupones de prueba de impedancia y planos de montaje.<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Key_Design_Takeaways\"><\/span><strong>Conclusiones clave sobre el dise\u00f1o<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<ol class=\"wp-block-list\">\n<li><strong>Esquema de apilamiento preferido 1<\/strong>, asegurando un plano de tierra adyacente a las capas de se\u00f1al primarias.<\/li>\n\n\n\n<li><strong>Equilibrar el coste y el rendimiento a trav\u00e9s del dise\u00f1o.<\/strong>, utilizando v\u00edas de alimentaci\u00f3n paralelas para reducir la impedancia.<\/li>\n\n\n\n<li><strong>Ruta que sigue el principio \u00abDif\u00edcil primero\u00bb<\/strong>, dando prioridad a las se\u00f1ales de alta velocidad en las capas internas.<\/li>\n\n\n\n<li><strong>Limitar la segmentaci\u00f3n de la energ\u00eda a 3 regiones.<\/strong>, colocando condensadores de desacoplamiento cerca de los circuitos integrados.<\/li>\n\n\n\n<li><strong>Validar con DRC y simulaci\u00f3n.<\/strong> para evitar tener que volver a trabajar en la posproducci\u00f3n.<\/li>\n<\/ol>","protected":false},"excerpt":{"rendered":"<p>An\u00e1lisis de los elementos fundamentales del dise\u00f1o de placas de circuito impreso de cuatro capas, incluyendo la selecci\u00f3n de apilamiento, el control de par\u00e1metros par\u00e1sitos, las estrategias de enrutamiento de alta velocidad y las t\u00e9cnicas de partici\u00f3n de potencia, junto con una lista de verificaci\u00f3n del dise\u00f1o para ayudar a los ingenieros a lograr dise\u00f1os de placas de circuito impreso de alta fiabilidad e integridad de se\u00f1al.<\/p>","protected":false},"author":2,"featured_media":8041,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[10],"tags":[66],"class_list":["post-8039","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-industry","tag-pcb-design"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v24.6 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>PCB Four-Layer Board Design - Topfastpcba<\/title>\n<meta name=\"description\" content=\"Four-layer PCB design encompasses optimized stackup schemes, via design, impedance control, and power integrity techniques. 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