{"id":8039,"date":"2025-10-18T17:41:49","date_gmt":"2025-10-18T09:41:49","guid":{"rendered":"https:\/\/topfastpcba.com\/?p=8039"},"modified":"2025-10-22T16:29:39","modified_gmt":"2025-10-22T08:29:39","slug":"pcb-four-layer-board-design","status":"publish","type":"post","link":"https:\/\/topfastpcba.com\/de\/pcb-four-layer-board-design\/","title":{"rendered":"PCB-Vierlagenplatinen-Design"},"content":{"rendered":"<p>In der Unterhaltungselektronik, bei industriellen Steuerungsger\u00e4ten und in digitalen Hochgeschwindigkeitssystemen werden vierlagige Leiterplatten aufgrund ihrer \u00fcberlegenen elektromagnetischen Vertr\u00e4glichkeit (EMV), Stromintegrit\u00e4t und Signalintegrit\u00e4t bevorzugt eingesetzt.<\/p>\n\n\n\n<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_75 counter-hierarchy ez-toc-counter ez-toc-custom ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Inhalts\u00fcbersicht<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/topfastpcba.com\/de\/pcb-four-layer-board-design\/#4-Layer_PCB_Stackup_Structure\" >4-Lagen-Leiterplatten-Stapelstruktur<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/topfastpcba.com\/de\/pcb-four-layer-board-design\/#Via_Design\" >\u00dcber Design<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/topfastpcba.com\/de\/pcb-four-layer-board-design\/#PCB_Routing\" >PCB-Routing<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/topfastpcba.com\/de\/pcb-four-layer-board-design\/#Power_Integrity_Design\" >Power Integrity Design<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/topfastpcba.com\/de\/pcb-four-layer-board-design\/#Design_Verification_Production_Preparation\" >Design\u00fcberpr\u00fcfung und Produktionsvorbereitung<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/topfastpcba.com\/de\/pcb-four-layer-board-design\/#Key_Design_Takeaways\" >Wichtige Erkenntnisse zum Design<\/a><\/li><\/ul><\/nav><\/div>\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"4-Layer_PCB_Stackup_Structure\"><\/span><a href=\"https:\/\/topfastpcba.com\/de\/4-layer-pcb-manufacturing-process\/\">4-Lagen PCB<\/a> Stapelstruktur<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Das Stackup-Design ist die Grundlage f\u00fcr die Leistung einer 4-lagigen Leiterplatte. Ein ungeeignetes Stackup kann zu Signal\u00fcbersprechen, Stromversorgungsrauschen und EMI-Nichtkonformit\u00e4t f\u00fchren.<\/p>\n\n\n\n<p><strong>1. Vergleich klassischer Stapelungsschemata<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Schema 1 (empfohlen)<\/strong>\n<ul class=\"wp-block-list\">\n<li>Oberste Schicht: Signalschicht<\/li>\n\n\n\n<li>Schicht 2: Massefl\u00e4che (GND)<\/li>\n\n\n\n<li>Schicht 3: Stromversorgungsebene (PWR)<\/li>\n\n\n\n<li>Unterste Schicht: Signalschicht<\/li>\n\n\n\n<li><strong>Vorteile:<\/strong> Die Grundplatte bietet eine solide Referenz f\u00fcr Signale der obersten Schicht. Die angrenzenden Strom- und Grundplatten bilden eine inh\u00e4rente Entkopplungskapazit\u00e4t.<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li><strong>Schema 2<\/strong>\n<ul class=\"wp-block-list\">\n<li>Oberste Schicht: Signalschicht<\/li>\n\n\n\n<li>Schicht 2: Stromversorgungsebene<\/li>\n\n\n\n<li>Schicht 3: Grundplatte<\/li>\n\n\n\n<li>Unterste Schicht: Signalschicht<\/li>\n\n\n\n<li><strong>Anwendbare Szenarien:<\/strong> Hochstromger\u00e4te (z. B. Motortreiber). Beachten Sie m\u00f6gliche \u00c4nderungen der Referenzebene f\u00fcr Signale der unteren Schicht.<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li><strong>Schema 3 (Mit Vorsicht verwenden)<\/strong>\n<ul class=\"wp-block-list\">\n<li>Oberste Schicht: Massefl\u00e4che<\/li>\n\n\n\n<li>Schicht 2: Signalschicht<\/li>\n\n\n\n<li>Schicht 3: Signalschicht<\/li>\n\n\n\n<li>Unterste Schicht: Leistungsebene<\/li>\n\n\n\n<li><strong>Risiken:<\/strong> Unvollst\u00e4ndige Massefl\u00e4che, lange Signalr\u00fcckwege. Vor allem f\u00fcr niederfrequente, steckverbinderdominierte Leiterplatten geeignet.<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n\n\n\n<p><strong>2. Einstellungen der wichtigsten Parameter<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Dielektrische Dicke:<\/strong> Recommended 0.1\u20130.2mm between signal and reference planes to enhance inter-layer coupling.<\/li>\n\n\n\n<li><strong>Kupfergewicht:<\/strong> Outer layers 1oz (35\u03bcm), inner layers 0.5oz (17.5\u03bcm). Can increase to 2oz for high-current areas.<\/li>\n\n\n\n<li><strong>R\u00fcckzugskonstruktion:<\/strong> Power planes should be indented 40\u201380mil relative to the ground plane (20H rule) to reduce edge radiation.<\/li>\n<\/ul>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"600\" height=\"402\" src=\"https:\/\/topfastpcba.com\/wp-content\/uploads\/2025\/10\/4-Layer-PCB.jpg\" alt=\"4-Lagen PCB\" class=\"wp-image-8040\" srcset=\"https:\/\/topfastpcba.com\/wp-content\/uploads\/2025\/10\/4-Layer-PCB.jpg 600w, https:\/\/topfastpcba.com\/wp-content\/uploads\/2025\/10\/4-Layer-PCB-300x201.jpg 300w, https:\/\/topfastpcba.com\/wp-content\/uploads\/2025\/10\/4-Layer-PCB-18x12.jpg 18w, https:\/\/topfastpcba.com\/wp-content\/uploads\/2025\/10\/4-Layer-PCB-150x101.jpg 150w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><\/figure>\n<\/div>\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Via_Design\"><\/span>\u00dcber Design<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Vias sind f\u00fcr Verbindungen zwischen Schichten von entscheidender Bedeutung, f\u00fchren jedoch zu parasit\u00e4ren Parametern, die Hochgeschwindigkeitssignale beeintr\u00e4chtigen.<\/p>\n\n\n\n<p><strong>1. \u00dcber die Typenauswahl<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Durchkontaktierungen:<\/strong> Kosteng\u00fcnstig, geeignet f\u00fcr Standard-Signale und Stromanschl\u00fcsse.<\/li>\n\n\n\n<li><strong>Blinde\/vergrabene Durchkontaktierungen:<\/strong> Wird f\u00fcr das Escape-Routing von BGAs mit hoher Dichte verwendet, erh\u00f6ht jedoch die Prozesskosten.<\/li>\n<\/ul>\n\n\n\n<p><strong>2. Berechnung parasit\u00e4rer Parameter<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Parasit\u00e4re Kapazit\u00e4t:<\/strong><br><code>C \u2248 1.41\u03b5 \u00b7 T \u00b7 D1 \/ (D2 - D1)<\/code><br>Wo <code>T<\/code> ist die Plattenst\u00e4rke, <code>D1<\/code> ist der Bohrerdurchmesser, <code>D2<\/code> ist der Durchmesser der Unterlage.<\/li>\n\n\n\n<li><strong>Parasit\u00e4re Induktivit\u00e4t:<\/strong><br><code>L \u2248 5.08h [ln(4h \/ d) + 1]<\/code><br>Wo <code>h<\/code> ist \u00fcber die L\u00e4nge, <code>d<\/code> ist der Bohrerdurchmesser.<\/li>\n<\/ul>\n\n\n\n<p><strong>3. \u00dcber Nutzungsrichtlinien<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Power-Vias:<\/strong> Verwenden Sie gr\u00f6\u00dfere Durchkontaktierungen (z. B. 12 mil Durchmesser\/16 mil Bohrung) und platzieren Sie mehrere parallel, um die Impedanz zu reduzieren.<\/li>\n\n\n\n<li><strong>Signal-Durchkontaktierungen:<\/strong> Bevorzugen Sie kleinere Durchkontaktierungen (z. B. 8 mil Durchmesser\/12 mil Bohrung). Vermeiden Sie asymmetrische Platzierungen in Differentialpaaren.<\/li>\n\n\n\n<li><strong>Thermische Durchkontaktierungen:<\/strong> Unter w\u00e4rmeerzeugende Komponenten legen (z. B. 0,3-mm-Bohrer, 1,5-mm-Raster).<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"PCB_Routing\"><\/span><a href=\"https:\/\/topfastpcba.com\/de\/pcb-routing-3w-principle\/\">PCB-Routing<\/a><span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p><strong>1. Routing-Verfahren<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Zuerst schwierige Bereiche angehen:<\/strong> Beginnen Sie mit dem Routing in komplexen Bereichen wie BGAs und Hochgeschwindigkeitsschnittstellen.<\/li>\n\n\n\n<li><strong>Modulares Handling:<\/strong> Routen nach Funktionsbl\u00f6cken (z. B. MCU, Speicher, analoge Schaltungen), um gegenseitige St\u00f6rungen zu vermeiden.<\/li>\n\n\n\n<li><strong>Aufr\u00e4umrouting:<\/strong> Leiten Sie Signale mit niedriger Geschwindigkeit zuletzt weiter und optimieren Sie die Kanalauslastung durch Anpassen der Leiterbahnbreite und des Abstands.<\/li>\n<\/ul>\n\n\n\n<p><strong>2. Kritische Routing-Regeln<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Impedanzregelung:<\/strong>\n<ul class=\"wp-block-list\">\n<li>Single-ended: 50\u03a9. Differential pairs: 100\u03a9.<\/li>\n\n\n\n<li>Erreichen Sie dies durch Anpassen der Leiterbahnbreite, der Dielektrizit\u00e4tskonstante und der Permittivit\u00e4t.<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li><strong>Hochgeschwindigkeits-Signalverarbeitung:<\/strong>\n<ul class=\"wp-block-list\">\n<li>Priorisieren Sie die Verlegung von Taktsignalen auf inneren Schichten, bezogen auf eine Massefl\u00e4che.<\/li>\n\n\n\n<li>Maintain length matching in differential pairs (\u22645mil tolerance).<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li><strong>Leistungsfl\u00e4chen-Segmentierung:<\/strong>\n<ul class=\"wp-block-list\">\n<li>Segmentieren Sie eine einzelne Stromversorgungsebene in maximal 3 Bereiche (z. B. 3,3 V, 5 V, 12 V).<\/li>\n\n\n\n<li>Use segmentation lines \u22650.5mm wide to prevent creepage issues.<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Power_Integrity_Design\"><\/span>Power Integrity Design<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p><strong>1. Platzierung des Entkopplungskondensators<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Auswahl:<\/strong> 0.1\u03bcF ceramic capacitors (high-frequency) + 10\u03bcF tantalum capacitors (low-frequency).<\/li>\n\n\n\n<li><strong>Platzierung:<\/strong> Position close to IC power pins (\u22643mm). Connect directly to power\/ground planes via vias.<\/li>\n<\/ul>\n\n\n\n<p><strong>2. Integrit\u00e4t der Grundplatte<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Vermeiden Sie eine Aufteilung der Massefl\u00e4che durch Signalleitungen, um niederohmige R\u00fcckwege zu gew\u00e4hrleisten.<\/li>\n\n\n\n<li>Connect digital and analog grounds at a single point using a ferrite bead or 0\u03a9 resistor.<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Design_Verification_Production_Preparation\"><\/span>Design\u00fcberpr\u00fcfung und Produktionsvorbereitung<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p><strong>1. DRC-Checkliste<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Trace Width\/Spacing: General signals \u22656\/6mil, Power traces \u226512\/12mil.<\/li>\n\n\n\n<li>Drill-to-Copper Distance: \u22658mil to prevent short circuits.<\/li>\n<\/ul>\n\n\n\n<p><strong>2. Signalintegrit\u00e4tssimulation<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Verwenden Sie Tools wie HyperLynx oder Sigrity, um Anstiegszeit, Klingeln und Impedanzkontinuit\u00e4t zu \u00fcberpr\u00fcfen.<\/li>\n\n\n\n<li>Konzentrieren Sie sich auf die \u00dcberpr\u00fcfung von Uhren, Differenzsignalen und Netzteilwelligkeit.<\/li>\n<\/ul>\n\n\n\n<p><strong>3. Ausgabe der Produktionsdatei<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Stellen Sie Gerber-Dateien (einschlie\u00dflich Ebenen, L\u00f6tmaske, Bohrung), Impedanztestcoupons und Montagezeichnungen bereit.<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Key_Design_Takeaways\"><\/span><strong>Wichtige Erkenntnisse zum Design<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<ol class=\"wp-block-list\">\n<li><strong>Bevorzugtes Stapelschema 1<\/strong>, wodurch eine Grundplatte neben den prim\u00e4ren Signalschichten gew\u00e4hrleistet wird.<\/li>\n\n\n\n<li><strong>Kosten und Leistung durch Design ausgleichen<\/strong>, unter Verwendung paralleler Stromdurchf\u00fchrungen zur Verringerung der Impedanz.<\/li>\n\n\n\n<li><strong>Route nach dem Prinzip \u201eDifficult First\u201c<\/strong>, wobei Hochgeschwindigkeitssignale auf den inneren Schichten priorisiert werden.<\/li>\n\n\n\n<li><strong>Begrenzen Sie die Stromsegmentierung auf 3 Regionen.<\/strong>, Entkopplungskondensatoren in der N\u00e4he von ICs platzieren.<\/li>\n\n\n\n<li><strong>Mit DRC und Simulation validieren<\/strong> um Nacharbeiten in der Postproduktion zu vermeiden.<\/li>\n<\/ol>","protected":false},"excerpt":{"rendered":"<p>Analyse der Kernelemente des vierlagigen PCB-Designs, einschlie\u00dflich der Auswahl des Lagenaufbaus, der Steuerung parasit\u00e4rer Parameter, Strategien f\u00fcr das Hochgeschwindigkeits-Routing und Techniken zur Leistungsaufteilung, zusammen mit einer Checkliste zur Design\u00fcberpr\u00fcfung, die Ingenieuren dabei hilft, hochzuverl\u00e4ssige und signalintegrierte Leiterplattendesigns zu erzielen.<\/p>","protected":false},"author":2,"featured_media":8041,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[10],"tags":[66],"class_list":["post-8039","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-industry","tag-pcb-design"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v24.6 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>PCB Four-Layer Board Design - Topfastpcba<\/title>\n<meta name=\"description\" content=\"Four-layer PCB design encompasses optimized stackup schemes, via design, impedance control, and power integrity techniques. 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